Hitherto, construction of such flat-panel displays has been approached in one of two principal ways:
The first approach uses a wafer of single crystal semiconductor material, usually silicon, as the rear electrode-bearing substrate of the display panel. The pixel control devices are integrated within this structure. Wrist-watch sized displays have been produced using this technique. Larger area panels using 20 cm diameter silicon wafers, are under current development. Even though this monolithic construction technology is well-advanced, there are drawbacks. The process of 20 cm diameter wafers is both difficult and expensive because of problems relating to crystal uniformity, wafer warpage, wafer handling, etc. Also the area of silicon required is greater than that of the panel display area; a large quantity of semiconductor material is required. (See `A 480.times.480 element dichrome display dye MOS LCD`, K Kasahara et al, Society for Information Display XIV 1983. Library of Congress Card No. 75-642555).
The second approach uses a thin film transistor technique; the rear substrate includes a film of polycrystalline or amorphous silicon in which transistors are embodied. Difficulties arise due to the poor characteristics of devices made in polycrystalline silicon, especially as regards to leakage of reverse biassed pn junctions. Displays have been produced using this technique, typically displays with no more than 4.times.10.sup.4 pixels, with most, but not all, pixels working. Much development will be required however, and many serious problems will need to be overcome, if working displays with .about.10.sup.6 pixels are to be achieved. (See `Silicon TFTs for Flat Panel Displays`, F. Morin, Proceedings of the 14th Conference (1982 International) on Solid state Devices, Tokyo 1980; Japanese Journal of Applied Physics 22 (1983) Supplement 22-1 pp 481-485. Related articles by other authors follow on pp 487-500).